Mohammad Arman Soleimani

Hello! I’m Arman, an undergrad in computer engineering at Sharif University of Technology. I have a fondness for computer architecture, which stems from my middle-school passion for electronics and tinkering with Arduinos.

My background mainly revolves around in-memory processing and memory architecture, on which I have two years of RA experience at IPM. Moreover, I have some experience with FPGAs, including a summer internship at EPFL, and hands-on experience with embedded systems.

I aspire to employ these experiences to research architectures and circuits for machine learning.

news

Sep 26, 2023	I received a band 8.5 in IELTS Academic
Aug 8, 2023	CoolDRAM received a best paper award at ISLPED ‘23 😊

selected publications

2023

ISLPED

CoolDRAM: An Energy-Efficient and Robust DRAM

Nezam Rohbani, Mohammad Arman Soleimani, and Hamid Sarbazi-Azad

In 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023

Abs URL Best Paper

DRAM is the most mature and widely-utilized memory structure as main memory in computing systems. However, energy dissipation and latency of DRAM are two of the most serious limiting factors of this technology. All DRAM main operations are initiated by a Precharge phase, which is time-consuming and power-hungry. This work proposes a novel DRAM cell access scheme that entirely eliminates Precharge phase from DRAM read, write, and refresh operations, with a very slight modification in commodity DRAM structure. The proposed DRAM design, called CoolDRAM, operates using a single extra cell row as reference cells. CoolDRAM reduces energy dissipation by about 34% on average, with a negligible area overhead of about 0.4%. The robustness of CoolDRAM against process variation and environmental noises is 61× and 1.78 × of the state-of-the-art, respectively, while maintaining the same power consumption and latency.

2022

DAC

PIPF-DRAM: processing in precharge-free DRAM

Nezam Rohbani, Mohammad Arman Soleimani, and Hamid Sarbazi-Azad

In Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022

Abs URL

To alleviate costly data communication among processing cores and memory modules, parallel processing-in-memory (PIM) is a promising approach which exploits the huge available internal memory bandwidth. High capacity, wide row size, and maturity of DRAM technology, make DRAM an alluring structure for PIM. However, dense layout, high process variation, and noise vulnerability of DRAMs make it very challenging to apply PIM for DRAMs in practice. This work proposes a PIM structure which eliminates these DRAM limitations, exploiting a precharge-free DRAM (PF-DRAM) structure. The proposed PIM structure, called PIPF-DRAM, performs parallel bitwise operations only by modifying control signal sequences in PF-DRAM, with almost zero structural and circuit modifications. Comparing the state-of-the-art PIM techniques, PIPF-DRAM is 4.2× more robust to process variation, 4.1% faster in average cycle time of operations, and consumes 66.1% less energy.