publications

2023

1. ISLPED

   CoolDRAM: An Energy-Efficient and Robust DRAM

   Nezam Rohbani, Mohammad Arman Soleimani, and Hamid Sarbazi-Azad

   In 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023

   Abs URL Best Paper

   DRAM is the most mature and widely-utilized memory structure as main memory in computing systems. However, energy dissipation and latency of DRAM are two of the most serious limiting factors of this technology. All DRAM main operations are initiated by a Precharge phase, which is time-consuming and power-hungry. This work proposes a novel DRAM cell access scheme that entirely eliminates Precharge phase from DRAM read, write, and refresh operations, with a very slight modification in commodity DRAM structure. The proposed DRAM design, called CoolDRAM, operates using a single extra cell row as reference cells. CoolDRAM reduces energy dissipation by about 34% on average, with a negligible area overhead of about 0.4%. The robustness of CoolDRAM against process variation and environmental noises is 61× and 1.78 × of the state-of-the-art, respectively, while maintaining the same power consumption and latency.

2. NocArc

   OCRA: An Oblivious Congested Region Avoiding Routing Algorithm for 3D NoCs

   Maede Safari, Nezam Rohbani, Mohammad Arman Soleimani, and Hamid Sarbazi-Azad

   In Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023

   Abs URL

   The Three-Dimensional Network on Chip (3D NoC) is an interconnection architecture designed to address the increasing communication demands between processing cores. However, as traffic and power density continues to rise, efficient traffic management and thermal regulation within these chips have become crucial issues. One common problem encountered in mesh-based NoC structures, regardless of the routing approach employed, is traffic congestion in the central region. This paper introduces a novel routing algorithm named an Oblivious Congested Region Avoiding Routing Algorithm (OCRA) to evenly distribute packet flow across the entire network.OCRA addresses the traffic imbalance by statically configuring specific routers located in the east and west of each layer in a 3D NoC using YXZ and YZX and configuring other routers using XYZ. This configuration aims to minimize traffic congestion in the network, reduce total queuing delay and improve packet latency. The paper explores various configurations for OCRA, and simulation results on a cycle-accurate simulator indicate that a specific configuration known as Pyramidical achieves a 51.67% improvement in traffic load distribution across the network. Additionally, this configuration reduces average queuing delay by 48.7% and improves the performance of the saturated 3D NoC by 35.24% with no impact on chip area.

2022

1. DAC

   PIPF-DRAM: processing in precharge-free DRAM

   Nezam Rohbani, Mohammad Arman Soleimani, and Hamid Sarbazi-Azad

   In Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022

   Abs URL

   To alleviate costly data communication among processing cores and memory modules, parallel processing-in-memory (PIM) is a promising approach which exploits the huge available internal memory bandwidth. High capacity, wide row size, and maturity of DRAM technology, make DRAM an alluring structure for PIM. However, dense layout, high process variation, and noise vulnerability of DRAMs make it very challenging to apply PIM for DRAMs in practice. This work proposes a PIM structure which eliminates these DRAM limitations, exploiting a precharge-free DRAM (PF-DRAM) structure. The proposed PIM structure, called PIPF-DRAM, performs parallel bitwise operations only by modifying control signal sequences in PF-DRAM, with almost zero structural and circuit modifications. Comparing the state-of-the-art PIM techniques, PIPF-DRAM is 4.2× more robust to process variation, 4.1% faster in average cycle time of operations, and consumes 66.1% less energy.